RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
25,935 commits
1,251 contributors

Rank

178 14

Started

2006-06-02 6,906 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 127 commits #410 31 contributors #225
Past 90 days 361 commits #515 70 contributors #203
Past 365 days 1,638 commits #462 194 contributors #196
Past 1095 days 7,002 commits #374 456 contributors #202
All time 25,935 commits 1,251 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
711 Arun Thomas
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711 Daniel Glöckner
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711 David Anders
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711 Hans-Erik Floryd
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711 Harald Welte
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711 Ivo Manca
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711 Lennert Buytenhek
0 0 0 0 2
711 Maxime COQUELIN
0 0 0 0 2
711 Michael Roth
0 0 0 0 2
711 Niklas Söderlund
0 0 0 0 2
711 Oleksandr Tymoshenko
0 0 0 0 2
711 Tim Sander
0 0 0 0 2
711 Uwe Kleine-König
0 0 0 0 2
711 Yegor Yefremov
0 0 0 0 2
711 ksyx
0 0 0 0 2
711 Andreas Sandberg
0 0 0 0 2
711 Karl Palsson
0 0 0 0 2
711 Alexandru Gagniuc
0 0 0 0 2
711 Christoph Muellner
0 0 0 0 2
711 Jae Hyun Yoo
0 0 0 0 2
Showing 721 to 740 of 1251 results
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Contributing Companies

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