RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
25,885 commits
1,248 contributors

Rank

187 27

Started

2006-06-02 6,902 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 126 commits #416 30 contributors #243
Past 90 days 343 commits #532 62 contributors #233
Past 365 days 1,638 commits #461 189 contributors #200
Past 1095 days 6,972 commits #377 453 contributors #201
All time 25,885 commits 1,248 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
542 Steven Chang
0 0 0 1 1
542 Luca Rufer
0 0 0 1 1
542 SydMontague
0 0 0 1 1
542 wangyanwen
0 0 0 1 1
542 Alexander Richardson
0 0 0 1 1
542 Aleksey Lotosh
0 0 0 1 1
542 Riya Jain
0 0 0 1 1
542 sanket
0 0 0 1 1
542 Karl Palsson
0 0 0 1 1
710 Jonathan Larmour
0 0 0 0 2
710 Alexander Stein
0 0 0 0 2
710 Alexandre TORGUE
0 0 0 0 2
710 Andrew Ruder
0 0 0 0 2
710 Jean-Christian de Rivaz
0 0 0 0 2
710 Jerome Forissier
0 0 0 0 2
710 Guido Guenther
0 0 0 0 2
710 Ewout ter Hoeven
0 0 0 0 2
710 Dongxue Zhang
0 0 0 0 2
710 Edward Forgacs
0 0 0 0 2
710 Arun Thomas
0 0 0 0 2
Showing 701 to 720 of 1248 results
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Contributing Companies

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