RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,245 commits
1,237 contributors

Rank

204 6

Started

2006-06-02 6,995 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 88 commits #555 28 contributors #250
Past 90 days 377 commits #441 59 contributors #239
Past 365 days 1,482 commits #506 174 contributors #222
Past 1095 days 7,011 commits #370 446 contributors #210
All time 25,245 commits 1,237 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
513 Riya Jain
0 0 0 1 1
513 sanket
0 0 0 1 1
513 Murali Vijayaraghavan
0 0 0 1 1
513 zhuangzhuangdad
0 0 0 1 1
513 Afonso Oliveira
0 0 0 1 1
513 Lowie Deferme
0 0 0 1 1
513 Mark Featherston
0 0 0 1 1
513 Timur Golubovich
0 0 0 1 1
513 Jonathan Forrest
0 0 0 1 1
513 Karl Palsson
0 0 0 1 1
691 John Zaitseff
0 0 0 0 2
691 Jonathan Larmour
0 0 0 0 2
691 Alexander Stein
0 0 0 0 2
691 Alexandre TORGUE
0 0 0 0 2
691 Andrew Ruder
0 0 0 0 2
691 Jean-Christian de Rivaz
0 0 0 0 2
691 Jerome Forissier
0 0 0 0 2
691 Guido Guenther
0 0 0 0 2
691 Ewout ter Hoeven
0 0 0 0 2
691 Dongxue Zhang
0 0 0 0 2
Showing 681 to 700 of 1237 results
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Contributing Companies

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