RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,245 commits
1,237 contributors

Rank

204 7

Started

2006-06-02 6,994 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 88 commits #553 28 contributors #250
Past 90 days 377 commits #439 59 contributors #237
Past 365 days 1,482 commits #506 174 contributors #222
Past 1095 days 7,011 commits #370 446 contributors #210
All time 25,245 commits 1,237 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
513 Piotr Wegrzyn
0 0 0 1 1
513 Lucas
0 0 0 1 1
513 Steven Chang
0 0 0 1 1
513 Luca Rufer
0 0 0 1 1
513 SydMontague
0 0 0 1 1
513 wangyanwen
0 0 0 1 1
513 Alexander Richardson
0 0 0 1 1
513 Solra Bizna
0 0 0 1 1
513 Ioan-Cristian CÎRSTEA
0 0 0 1 1
513 Ioan-Cristian
0 0 0 1 1
513 Patrick Yingxi Pan
0 0 0 1 1
513 Aleksey Lotosh
0 0 0 1 1
513 Mudassir Ali
0 0 0 1 1
513 albert-azcarate
0 0 0 1 1
513 Guanghui Cheng
0 0 0 1 1
513 Guanghui Cheng
0 0 0 1 1
513 Paul Clarke
0 0 0 1 1
513 Bartosz Gasiorzewski
0 0 0 1 1
513 xyyy1420
0 0 0 1 1
513 Nyembezi Nyirongo
0 0 0 1 1
Showing 661 to 680 of 1237 results
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Contributing Companies

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