RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
25,873 commits
1,246 contributors

Rank

187 26

Started

2006-06-02 6,902 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 126 commits #419 30 contributors #242
Past 90 days 343 commits #532 62 contributors #233
Past 365 days 1,638 commits #461 189 contributors #200
Past 1095 days 6,972 commits #377 453 contributors #201
All time 25,873 commits 1,246 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
540 OOHehir
0 0 0 1 1
540 rmsyn
0 0 0 1 1
540 Davide Schiavone
0 0 0 1 1
540 Tomas Deingruber
0 0 0 1 1
540 Kai Schmitz
0 0 0 1 1
540 Jinyan Xu
0 0 0 1 1
540 Fei Yang
0 0 0 1 1
540 lpha-z
0 0 0 1 1
540 Liana Koleva
0 0 0 1 1
540 allen1130
0 0 0 1 1
540 Shao-Ce SUN
0 0 0 1 1
540 Felix Hauptmann
0 0 0 1 1
540 andy_a
0 0 0 1 1
540 yf13
0 0 0 1 1
540 Yu Chien Peter Lin
0 0 0 1 1
540 phanirajkiran
0 0 0 1 1
540 Amaury Pouly
0 0 0 1 1
540 Phil Kirkpatrick
0 0 0 1 1
540 Samadou OURO-AGOROUKO
0 0 0 1 1
540 Ahmed Boughanmi
0 0 0 1 1
Showing 661 to 680 of 1246 results
Previous Next

Contributing Companies

Add the OSSRank badge to this project

OSSRank Badge Add this OSSRank shield to your project's README.md
[![OSSRank](https://shields.io/endpoint?url=https://ossrank.com/shield/1311)](https://ossrank.com/p/1311)