RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
25,873 commits
1,246 contributors

Rank

188 25

Started

2006-06-02 6,901 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 126 commits #419 30 contributors #243
Past 90 days 343 commits #532 62 contributors #233
Past 365 days 1,638 commits #461 189 contributors #200
Past 1095 days 6,972 commits #377 453 contributors #201
All time 25,873 commits 1,246 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
540 Justin Hammond
0 0 0 1 1
540 Adrien Grassein
0 0 0 1 1
540 MadSquirrel
0 0 0 1 1
540 Dongjie Xie
0 0 0 1 1
540 Frank Dischner
0 0 0 0 3
540 Martin Hierholzer
0 0 0 1 1
540 Abdul Wadood
0 0 0 1 1
540 Xavier Esteve
0 0 0 1 1
540 Dan Stahlke
0 0 0 1 1
540 Fawaz Tirmizi
0 0 0 1 1
540 Giulio Fieramosca
0 0 0 1 1
540 Nima Palizban
0 0 0 1 1
540 Simon Smiganovski
0 0 0 1 1
540 Billy Traynor
0 0 0 1 1
540 Thiemo van Engelen
0 0 0 1 1
540 Michael Sammler
0 0 0 1 1
540 Fei Yang
0 0 0 1 1
540 Thomas Hepworth
0 0 0 1 1
540 Bruno Mendes
0 0 0 1 1
540 Shih-Sheng Yang
0 0 0 1 1
Showing 641 to 660 of 1246 results
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Contributing Companies

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