RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,245 commits
1,237 contributors

Rank

212 15

Started

2006-06-02 6,994 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 91 commits #539 26 contributors #275
Past 90 days 373 commits #443 57 contributors #243
Past 365 days 1,477 commits #511 173 contributors #222
Past 1095 days 7,006 commits #372 446 contributors #210
All time 25,245 commits 1,237 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
513 Amaury Pouly
0 0 0 1 1
513 Phil Kirkpatrick
0 0 0 1 1
513 Samadou OURO-AGOROUKO
0 0 0 1 1
513 Ahmed Boughanmi
0 0 0 1 1
513 Brandon Pupp
0 0 0 1 1
513 Fedi Bouzazi
0 0 0 1 1
513 Luca Hung
0 0 0 1 1
513 Gabriele Tripi
0 0 0 1 1
513 Nikola Lukić
0 0 0 1 1
513 xyq1113723547
0 0 0 1 1
513 saahm
0 0 0 1 1
513 Roy Franz
0 0 0 1 1
513 Samuel Dewan
0 0 0 1 1
513 Abhinav Srivastava
0 0 0 1 1
513 mylai-mtk
0 0 0 1 1
513 akshaykumars614
0 0 0 1 1
513 splinedrive
0 0 0 1 1
513 OccupyMars2025
0 0 0 1 1
513 Yaksis
0 0 0 1 1
513 NaOHCC
0 0 0 1 1
Showing 641 to 660 of 1237 results
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Contributing Companies

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