RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,240 commits
1,237 contributors

Rank

212 15

Started

2006-06-02 6,994 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 91 commits #541 26 contributors #275
Past 90 days 373 commits #443 57 contributors #243
Past 365 days 1,477 commits #510 173 contributors #223
Past 1095 days 7,006 commits #372 446 contributors #210
All time 25,240 commits 1,237 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
513 Thomas Hepworth
0 0 0 1 1
513 hiagofranco
0 0 0 1 1
513 Bruno Mendes
0 0 0 1 1
513 Shih-Sheng Yang
0 0 0 1 1
513 OOHehir
0 0 0 1 1
513 rmsyn
0 0 0 1 1
513 Davide Schiavone
0 0 0 1 1
513 Tomas Deingruber
0 0 0 1 1
513 Kai Schmitz
0 0 0 1 1
513 Jinyan Xu
0 0 0 1 1
513 Fei Yang
0 0 0 1 1
513 lpha-z
0 0 0 1 1
513 Liana Koleva
0 0 0 1 1
513 allen1130
0 0 0 1 1
513 Shao-Ce SUN
0 0 0 1 1
513 Felix Hauptmann
0 0 0 1 1
513 andy_a
0 0 0 1 1
513 yf13
0 0 0 1 1
513 Yu Chien Peter Lin
0 0 0 1 1
513 phanirajkiran
0 0 0 1 1
Showing 621 to 640 of 1237 results
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Contributing Companies

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