RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
25,873 commits
1,246 contributors

Rank

188 24

Started

2006-06-02 6,901 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 126 commits #416 30 contributors #242
Past 90 days 343 commits #530 62 contributors #232
Past 365 days 1,638 commits #461 189 contributors #200
Past 1095 days 6,972 commits #377 453 contributors #201
All time 25,873 commits 1,246 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
540 Zhen Wei
0 0 0 0 3
540 Asier Llano
0 0 0 1 1
540 Jerry Zhao
0 0 0 1 1
540 Robot
0 0 0 1 1
540 =
0 0 0 1 1
540 Wenting Zhang
0 0 0 1 1
540 Emmanuel Blot
0 0 0 1 1
540 Christoph Müllner
0 0 0 1 1
540 frankplow
0 0 0 1 1
540 Lawrence Hunter
0 0 0 1 1
540 4vtomat
0 0 0 1 1
540 stnolting
0 0 0 1 1
540 Jesús Sanz del Rey
0 0 0 1 1
540 Yang sheng
0 0 0 1 1
540 Adrian Harris
0 0 0 1 1
540 JamesKenneyImperas
0 0 0 1 1
540 Deheng Yang
0 0 0 1 1
540 Robert Norton
0 0 0 1 1
540 Charalampos Mitrodimas
0 0 0 1 1
540 Sharafat
0 0 0 1 1
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Contributing Companies

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