RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,237 commits
1,235 contributors

Rank

214 17

Started

2006-06-02 6,993 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 91 commits #545 25 contributors #287
Past 90 days 370 commits #442 55 contributors #248
Past 365 days 1,476 commits #513 173 contributors #224
Past 1095 days 7,009 commits #372 445 contributors #211
All time 25,237 commits 1,235 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
513 Bernhard Rosenkränzer
0 0 0 1 1
513 JamesKenneyImperas
0 0 0 1 1
513 Deheng Yang
0 0 0 1 1
513 Robert Norton
0 0 0 1 1
513 Charalampos Mitrodimas
0 0 0 1 1
513 Sharafat
0 0 0 1 1
513 Justin Hammond
0 0 0 1 1
513 Dongjie Xie
0 0 0 1 1
513 Frank Dischner
0 0 0 0 3
513 Matt Trescott
0 0 0 1 1
513 Abdul Wadood
0 0 0 1 1
513 Xavier Esteve
0 0 0 1 1
513 Dan Stahlke
0 0 0 1 1
513 Fawaz Tirmizi
0 0 0 1 1
513 Giulio Fieramosca
0 0 0 1 1
513 Nima Palizban
0 0 0 1 1
513 Simon Smiganovski
0 0 0 1 1
513 Billy Traynor
0 0 0 1 1
513 Thiemo van Engelen
0 0 0 1 1
513 Michael Sammler
0 0 0 1 1
Showing 601 to 620 of 1235 results
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Contributing Companies

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