RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
26,111 commits
1,262 contributors

Rank

195 7

Started

2006-06-02 6,945 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 104 commits #480 27 contributors #259
Past 90 days 378 commits #468 65 contributors #218
Past 365 days 1,537 commits #489 181 contributors #209
Past 1095 days 7,014 commits #375 457 contributors #200
All time 26,111 commits 1,262 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
21 Evgeniy Naydanov
0 9 77 105 105
22 Evgeniy Naydanov
0 2 48 142 142
23 zwelch
0 0 0 0 565
24 Oyvind Harboe
0 0 0 0 538
25 David Brownell
0 0 0 0 531
26 Kersten Richter
3 3 42 125 125
27 Paul Fertser
0 0 2 11 407
28 Nicolas Brunie
0 0 6 130 130
29 Megan Wachs
0 0 0 0 398
30 ntfreak
0 0 0 0 324
31 Andreas Fritiofson
0 0 0 1 252
32 Alex Richardson
0 11 23 42 42
33 Erhan Kurubas
0 0 0 64 80
34 Anatoly Parshintsev
0 0 22 45 45
35 Tarek BOCHKATI
0 0 0 4 179
36 Ved Shanbhogue
0 0 19 42 44
37 Andreas Cord-Landwehr
0 0 0 59 59
38 Alistair Francis
0 0 0 3 170
39 Matthias Welwarsky
0 0 0 0 173
40 Alasdair
0 1 8 33 74
Showing 21 to 40 of 1262 results
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Contributing Companies

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