RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,236 commits
1,235 contributors

Rank

206 9

Started

2006-06-02 6,991 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 102 commits #491 27 contributors #269
Past 90 days 377 commits #440 55 contributors #250
Past 365 days 1,495 commits #506 176 contributors #221
Past 1095 days 7,007 commits #373 445 contributors #209
All time 25,236 commits 1,235 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
21 Evgeniy Naydanov
0 1 41 143 143
22 Oyvind Harboe
0 0 0 0 538
23 David Brownell
0 0 0 0 531
24 Evgeniy Naydanov
0 1 66 106 106
25 Marc Schink
0 0 29 101 224
26 Kersten Richter
1 4 22 126 126
27 Paul Fertser
0 0 2 11 407
28 Nicolas Brunie
0 0 6 130 130
29 Megan Wachs
0 0 0 0 398
30 ntfreak
0 0 0 0 324
31 Andreas Fritiofson
0 0 0 1 252
32 Nadime Barhoumi
8 16 23 23 23
33 Alper Ak
6 18 18 19 19
34 Alex Richardson
0 2 23 42 42
35 Anatoly Parshintsev
0 0 20 45 45
36 Erhan Kurubas
0 0 0 56 80
37 Tarek BOCHKATI
0 0 0 4 179
38 Andreas Cord-Landwehr
0 0 0 59 59
39 Matthias Welwarsky
0 0 0 0 173
39 Alistair Francis
0 0 0 3 167
Showing 21 to 40 of 1235 results
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Contributing Companies

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