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OSS Project

Chisel

An open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs

Rank
883
Increased by 43
Git Repositories
chisel3
Started
2015-04-27 3,527 days ago
Categories
Computer Architecture
GitHub Stars
4,037 #1,975
Stackoverflow Questions with tag chisel
694 #563
Weekly commits since inception
2015 2019 2024
Weekly contributors since inception
2015 2019 2024
Recent Project Activity
Day Span Commits Contributors
30 41 #964 9 #789
90 124 #1,063 20 #746
365 528 #1,140 43 #943
1095 1,451 #1,368 79 #1,257
All time 3,319 147
Contributing Individuals
Commits past X days
Contributor 30 90 All
1 Jack Koenig
SiFive
7 22 702
2 Schuyler Eldridge
SiFive
16 29 343
3 Jiuyang Liu 2 4 140
4 Chisel Bot 7 15 56
5 Jim Lawson
University of California, Berkeley
0 0 319
6 Andrew Waterman
SiFive
0 0 259
7 Megan Wachs 0 1 75
8 Will Dietz
SiFive
0 5 42
9 Aditya Naik 2 10 44
10 Ducky 0 0 199
11 Schuyler Eldridge 0 0 168
12 Chick Markley 0 0 110
13 Adam Izraelevitz 0 2 79
14 unlsycn 4 12 12
15 Deborah Soung 0 2 32
16 Aditya Naik 0 10 18
17 Sprite 0 2 21
18 Mike Urbach 0 0 20
19 Jared Barocsi 0 0 32
20 Mike Urbach 0 0 21
Contributing Companies

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