RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,181 commits
1,231 contributors

Rank

194 8

Started

2006-06-02 6,976 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 137 commits #353 24 contributors #299
Past 90 days 388 commits #441 56 contributors #251
Past 365 days 1,533 commits #500 178 contributors #217
Past 1095 days 6,996 commits #373 449 contributors #206
All time 25,181 commits 1,231 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
805 Manuel Wick
0 0 0 0 1
805 Gurjeet Singh
0 0 0 0 1
805 Stephan Nolting
0 0 0 0 1
805 Salvatore Giorgio PECORINO
0 0 0 0 1
805 Ben Bender
0 0 0 0 1
805 MadSquirrel
0 0 0 0 1
805 Martin Hierholzer
0 0 0 0 1
805 James G. Smith
0 0 0 0 1
805 Muhammad Bilal Sakhawat
0 0 0 0 1
805 David Vidrie Leon
0 0 0 0 1
805 Tobias Diedrich
0 0 0 0 1
Showing 1221 to 1231 of 1231 results
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Contributing Companies

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