RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,181 commits
1,231 contributors

Rank

194 8

Started

2006-06-02 6,976 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 137 commits #353 24 contributors #299
Past 90 days 388 commits #441 56 contributors #251
Past 365 days 1,533 commits #500 178 contributors #217
Past 1095 days 6,996 commits #373 449 contributors #206
All time 25,181 commits 1,231 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
517 HowJMay
0 0 0 1 1
517 AdamLatos
0 0 0 1 1
517 Hesham Almatary
0 0 0 0 3
517 Graeme Smecher
0 0 0 1 1
517 Gianluca Renzi
0 0 0 0 3
517 Nidal Faour
0 0 0 0 3
517 Gaëtan Carlier
0 0 0 0 3
517 Daniel Serpell
0 0 0 1 1
517 Catalin Patulea
0 0 0 0 3
517 Ulf Wetzker
0 0 0 0 3
517 Artur Rojek
0 0 0 1 1
517 Boris-Chengbiao Zhou
0 0 0 1 1
517 Bin Meng
0 0 0 1 1
517 Bill Traynor
0 0 0 1 1
517 Forest Crossman
0 0 0 0 3
517 Jiafei Pan
0 0 0 1 1
517 Andrey Skvortsov
0 0 0 0 3
517 Christoph Müllner
0 0 0 1 1
517 Jonathan Bell
0 0 0 1 1
517 Kyle Schwarz
0 0 0 1 1
Showing 581 to 600 of 1231 results
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Contributing Companies

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