RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,191 commits
1,232 contributors

Rank

193 8

Started

2006-06-02 6,976 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 147 commits #353 25 contributors #299
Past 90 days 387 commits #441 55 contributors #251
Past 365 days 1,539 commits #500 179 contributors #217
Past 1095 days 7,004 commits #373 450 contributors #206
All time 25,191 commits 1,232 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
518 Keith Packard
0 0 0 1 1
518 HowJMay
0 0 0 1 1
518 Hesham Almatary
0 0 0 0 3
518 Graeme Smecher
0 0 0 1 1
518 Gianluca Renzi
0 0 0 0 3
518 Carsten Gosvig
0 0 0 0 3
518 Gaëtan Carlier
0 0 0 0 3
518 Daniel Serpell
0 0 0 1 1
518 Catalin Patulea
0 0 0 0 3
518 Christopher Pulte
0 0 0 0 3
518 Artur Rojek
0 0 0 1 1
518 Boris-Chengbiao Zhou
0 0 0 1 1
518 Bin Meng
0 0 0 1 1
518 Jean-Christian de Rivaz
0 0 0 0 3
518 Bill Traynor
0 0 0 1 1
518 Forest Crossman
0 0 0 0 3
518 Jiafei Pan
0 0 0 1 1
518 Andrey Skvortsov
0 0 0 0 3
518 Jonathan Bell
0 0 0 1 1
518 Kyle Schwarz
0 0 0 1 1
Showing 561 to 580 of 1232 results
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Contributing Companies

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