RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,234 commits
1,235 contributors

Rank

206 8

Started

2006-06-02 6,991 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 102 commits #490 27 contributors #266
Past 90 days 377 commits #440 55 contributors #250
Past 365 days 1,495 commits #508 176 contributors #222
Past 1095 days 7,007 commits #373 445 contributors #209
All time 25,234 commits 1,235 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
515 Kian-Meng Ang
0 0 0 1 1
515 Keith Packard
0 0 0 1 1
515 HowJMay
0 0 0 1 1
515 Hesham Almatary
0 0 0 0 3
515 Graeme Smecher
0 0 0 1 1
515 Christopher Pulte
0 0 0 0 3
515 Gianluca Renzi
0 0 0 0 3
515 Gaëtan Carlier
0 0 0 0 3
515 Daniel Serpell
0 0 0 1 1
515 Jean-Christian de Rivaz
0 0 0 0 3
515 Catalin Patulea
0 0 0 0 3
515 Artur Rojek
0 0 0 1 1
515 Boris-Chengbiao Zhou
0 0 0 1 1
515 Jonas Hoerberg
0 0 0 0 3
515 Bin Meng
0 0 0 1 1
515 Bill Traynor
0 0 0 1 1
515 Forest Crossman
0 0 0 0 3
515 Jiafei Pan
0 0 0 1 1
515 Andrey Skvortsov
0 0 0 0 3
515 Jonathan Bell
0 0 0 1 1
Showing 561 to 580 of 1235 results
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Contributing Companies

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