RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
25,873 commits
1,246 contributors

Rank

188 23

Started

2006-06-02 6,901 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 126 commits #420 30 contributors #242
Past 90 days 343 commits #531 62 contributors #231
Past 365 days 1,638 commits #460 189 contributors #200
Past 1095 days 6,972 commits #376 453 contributors #201
All time 25,873 commits 1,246 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
540 Keith Packard
0 0 0 1 1
540 HowJMay
0 0 0 1 1
540 Hesham Almatary
0 0 0 0 3
540 Graeme Smecher
0 0 0 1 1
540 Gianluca Renzi
0 0 0 0 3
540 dramforever
0 0 0 1 1
540 Gaëtan Carlier
0 0 0 0 3
540 Daniel Serpell
0 0 0 1 1
540 Catalin Patulea
0 0 0 0 3
540 Mete Balci
0 0 0 0 3
540 Artur Rojek
0 0 0 1 1
540 Boris-Chengbiao Zhou
0 0 0 1 1
540 Bin Meng
0 0 0 1 1
540 Meng Zhuo
0 0 0 1 1
540 Forest Crossman
0 0 0 0 3
540 Jia-Wei Chen
0 0 0 1 1
540 Andrey Skvortsov
0 0 0 0 3
540 Alvin Šipraga
0 0 0 1 1
540 Jonathan Bell
0 0 0 1 1
540 Kyle Schwarz
0 0 0 1 1
Showing 561 to 580 of 1246 results
Previous Next

Contributing Companies

Add the OSSRank badge to this project

OSSRank Badge Add this OSSRank shield to your project's README.md
[![OSSRank](https://shields.io/endpoint?url=https://ossrank.com/shield/1311)](https://ossrank.com/p/1311)