RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,232 commits
1,235 contributors

Rank

200 2

Started

2006-06-02 6,990 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 101 commits #480 27 contributors #263
Past 90 days 378 commits #442 55 contributors #252
Past 365 days 1,497 commits #506 176 contributors #222
Past 1095 days 7,008 commits #372 446 contributors #209
All time 25,232 commits 1,235 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
516 Lorenz Brun
0 0 0 1 1
516 Kian-Meng Ang
0 0 0 1 1
516 Keith Packard
0 0 0 1 1
516 HowJMay
0 0 0 1 1
516 Hesham Almatary
0 0 0 0 3
516 Graeme Smecher
0 0 0 1 1
516 Gianluca Renzi
0 0 0 0 3
516 Gaëtan Carlier
0 0 0 0 3
516 Daniel Serpell
0 0 0 1 1
516 Catalin Patulea
0 0 0 0 3
516 Artur Rojek
0 0 0 1 1
516 Boris-Chengbiao Zhou
0 0 0 1 1
516 Bin Meng
0 0 0 1 1
516 Maxim Sergeev
0 0 0 1 1
516 Bill Traynor
0 0 0 1 1
516 Forest Crossman
0 0 0 0 3
516 Jiafei Pan
0 0 0 1 1
516 Pierre Kuo
0 0 0 0 3
516 Andrey Skvortsov
0 0 0 0 3
516 Jonathan Bell
0 0 0 1 1
Showing 521 to 540 of 1235 results
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Contributing Companies

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