RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
25,873 commits
1,246 contributors

Rank

188 20

Started

2006-06-02 6,899 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 126 commits #424 30 contributors #248
Past 90 days 343 commits #529 62 contributors #233
Past 365 days 1,638 commits #465 189 contributors #200
Past 1095 days 6,972 commits #376 453 contributors #202
All time 25,873 commits 1,246 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
314 Simon Barner
0 0 0 0 8
314 Bilal Sakhawat
0 0 0 1 6
314 Ernie Edgar
0 0 0 0 8
314 Peter A. Bigot
0 0 0 0 8
314 Marc Pignat
0 0 0 0 8
326 Gleb Gagarin
0 0 0 0 7
326 Florian Zaruba
0 0 0 1 5
326 David Horner
0 0 0 0 7
326 Chih-Min Chao
0 0 0 0 7
326 Greg Savin
0 0 0 0 7
326 Alexey Fisher
0 0 0 0 7
326 Yueh-Ting Chen
0 0 0 2 3
326 Han-Kuan Chen
0 0 0 0 7
326 Torbjørn Viem Ness
0 0 0 1 5
326 Craig Topper
0 0 0 2 3
326 Sunil V L
0 0 0 0 7
326 Robert Jarzmik
0 0 0 0 7
326 Jubilee Young TCDI
0 0 1 1 2
326 David Ung
0 0 0 0 7
326 Jim Paris
0 0 0 0 7
Showing 321 to 340 of 1246 results
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Contributing Companies

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