RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,232 commits
1,235 contributors

Rank

195 2

Started

2006-06-02 6,988 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 107 commits #462 28 contributors #253
Past 90 days 385 commits #442 57 contributors #244
Past 365 days 1,505 commits #503 176 contributors #224
Past 1095 days 7,021 commits #372 448 contributors #206
All time 25,232 commits 1,235 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
265 Kito Cheng SiFive
0 0 0 0 9
265 Dongchuan Zhang
0 0 1 2 2
265 Kamal Dasu
0 0 0 0 9
265 Alexandre Pereira da Silva
0 0 0 0 9
305 Peter A. Bigot
0 0 0 0 8
305 Ake Rehnman
0 0 0 0 8
305 Marc Pignat
0 0 0 0 8
305 sb-sf
0 0 0 0 8
305 Nathaniel Wesley Filardo
0 0 0 0 8
305 Angus Gratton
0 0 0 0 8
305 Luca Bruno
0 0 0 0 8
305 Jian-Hong Pan
0 0 0 2 4
305 Simon Barner
0 0 0 0 8
305 Ernie Edgar
0 0 0 0 8
315 Torbjørn Viem Ness
0 0 0 1 5
315 Craig Topper
0 0 0 2 3
315 Robert Jarzmik
0 0 0 0 7
315 Jubilee Young TCDI
0 0 1 1 2
315 David Ung
0 0 0 0 7
315 Jim Paris
0 0 0 0 7
Showing 301 to 320 of 1235 results
Previous Next

Contributing Companies

Add the OSSRank badge to this project

OSSRank Badge Add this OSSRank shield to your project's README.md
[![OSSRank](https://shields.io/endpoint?url=https://ossrank.com/shield/1311)](https://ossrank.com/p/1311)