RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
26,007 commits
1,255 contributors

Rank

207 24

Started

2006-06-02 6,925 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 92 commits #517 23 contributors #305
Past 90 days 340 commits #531 66 contributors #216
Past 365 days 1,549 commits #491 183 contributors #207
Past 1095 days 6,964 commits #376 454 contributors #202
All time 26,007 commits 1,255 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
1 Bill Traynor
12 21 82 1,712 1,730
2 Andrew Waterman SiFive
5 35 182 525 1,869
3 Tim Newsome SiFive
0 0 0 501 2,052
4 Antonio Borneo STMicroelectronics
0 6 98 407 1,263
5 Krste Asanovic SiFive
0 0 0 126 1,071
6 Øyvind Harboe Ascenium
0 0 0 0 1,224
7 Tariq Kurd Codasip
0 0 0 44 847
8 Tim Hutt
7 26 105 141 141
9 Ken Dockser Rivos
0 0 0 269 297
10 Tomas Vanek
0 1 20 143 439
11 Dan Smathers Seagate
0 0 0 221 337
12 Jordan Carlin
13 36 88 95 95
13 Prashanth Mundkur
8 20 24 24 509
14 Ben Marshall PQShield
0 0 0 0 713
15 Khem Raj Comcast
0 2 16 101 370
16 Evgeniy Naydanov
0 14 82 105 105
17 Evgeniy Naydanov
0 4 57 142 142
18 Marc Schink
0 0 59 102 224
19 Zach Welch
0 0 0 0 604
20 Spencer Oliver
0 0 0 0 603
Showing 1 to 20 of 1255 results
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Contributing Companies

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