RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
25,932 commits
1,251 contributors

Rank

178 15

Started

2006-06-02 6,905 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 127 commits #410 31 contributors #225
Past 90 days 361 commits #516 70 contributors #203
Past 365 days 1,638 commits #464 194 contributors #196
Past 1095 days 7,002 commits #374 456 contributors #202
All time 25,932 commits 1,251 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
1 Bill Traynor
1 12 78 1,701 1,719
2 Andrew Waterman SiFive
25 36 196 535 1,866
3 Tim Newsome SiFive
0 0 0 519 2,052
4 Antonio Borneo STMicroelectronics
1 7 113 410 1,263
5 Krste Asanovic SiFive
0 0 0 147 1,071
6 Øyvind Harboe Ascenium
0 0 0 0 1,224
7 Tariq Kurd Codasip
0 0 0 47 847
8 Tim Hutt
11 35 107 135 135
9 Ken Dockser Rivos
0 0 0 269 297
10 Tomas Vanek
0 8 21 146 439
11 Dan Smathers Seagate
0 0 0 229 337
12 Jordan Carlin
20 30 82 84 84
13 Ben Marshall PQShield
0 0 0 0 713
14 Prashanth Mundkur
7 18 18 18 503
15 Evgeniy Naydanov
2 12 68 142 142
16 Tim Newsome
0 6 53 162 164
16 Evgeniy Naydanov
2 22 86 105 105
18 Khem Raj Comcast
2 2 17 107 370
19 Kersten Richter
0 1 88 122 122
20 Marc Schink
0 1 65 102 224
Showing 1 to 20 of 1251 results
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Contributing Companies

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