RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,234 commits
1,235 contributors

Rank

203 5

Started

2006-06-02 6,991 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 102 commits #488 27 contributors #264
Past 90 days 377 commits #440 55 contributors #251
Past 365 days 1,495 commits #508 176 contributors #222
Past 1095 days 7,007 commits #373 445 contributors #209
All time 25,234 commits 1,235 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
1 Bill Traynor
5 24 71 1,723 1,741
2 Andrew Waterman SiFive
8 24 132 521 1,749
3 Tim Newsome SiFive
0 0 0 486 1,915
4 Antonio Borneo STMicroelectronics
0 0 79 365 1,263
5 Tim Hutt
22 63 154 198 198
6 Øyvind Harboe Ascenium
0 0 0 0 1,224
7 Krste Asanovic SiFive
0 0 0 72 987
8 Prashanth Mundkur
11 33 50 50 535
9 Tariq Kurd Codasip
0 0 0 37 847
10 Christian Herber
7 61 98 98 98
11 Ken Dockser Rivos
0 0 0 269 289
12 Jordan Carlin
7 30 102 113 113
13 Tomas Vanek
0 0 16 136 439
14 Dan Smathers Seagate
0 0 0 207 336
15 Ben Marshall PQShield
0 0 0 0 706
16 Khem Raj Comcast
0 2 13 99 372
17 Zach Welch
0 0 0 0 604
18 Spencer Oliver
0 0 0 0 603
19 zwelch
0 0 0 0 565
20 Tim Newsome
0 0 25 162 164
Showing 1 to 20 of 1235 results
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Contributing Companies

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