RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
25,984 commits
1,254 contributors

Rank

193 13

Started

2006-06-02 6,918 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 100 commits #491 28 contributors #260
Past 90 days 369 commits #502 70 contributors #204
Past 365 days 1,607 commits #474 189 contributors #202
Past 1095 days 6,969 commits #375 454 contributors #203
All time 25,984 commits 1,254 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
1 Bill Traynor
8 18 82 1,708 1,726
2 Andrew Waterman SiFive
4 36 186 526 1,868
3 Tim Newsome SiFive
0 0 0 510 2,052
4 Antonio Borneo STMicroelectronics
0 6 109 407 1,263
5 Krste Asanovic SiFive
0 0 0 127 1,071
6 Øyvind Harboe Ascenium
0 0 0 0 1,224
7 Tariq Kurd Codasip
0 0 0 47 847
8 Tim Hutt
9 31 109 138 138
9 Ken Dockser Rivos
0 0 0 269 297
10 Tomas Vanek
0 4 21 143 439
11 Dan Smathers Seagate
0 0 0 221 337
12 Jordan Carlin
15 33 90 92 92
13 Ben Marshall PQShield
0 0 0 0 713
14 Prashanth Mundkur
5 19 21 21 506
15 Evgeniy Naydanov
0 12 67 142 142
16 Tim Newsome
0 6 50 162 164
17 Khem Raj Comcast
2 2 17 101 370
18 Evgeniy Naydanov
1 17 84 105 105
19 Marc Schink
0 1 59 102 224
20 Zach Welch
0 0 0 0 604
Showing 1 to 20 of 1254 results
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Contributing Companies

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