RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
25,998 commits
1,255 contributors

Rank

190 15

Started

2006-06-02 6,920 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 106 commits #464 27 contributors #271
Past 90 days 367 commits #493 69 contributors #204
Past 365 days 1,612 commits #470 189 contributors #202
Past 1095 days 6,968 commits #375 455 contributors #203
All time 25,998 commits 1,255 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
354 Atish Patra
0 0 0 0 6
354 Matt Lawson
0 0 1 1 1
354 Bill Traynor
0 0 0 2 2
354 François LEGAL
0 0 0 2 2
354 Eric Biggers
0 0 1 1 1
354 Jiafei Pan
0 0 1 1 1
354 Alexandre Ghiti
0 0 0 2 2
354 Alan Bowman
0 0 0 0 6
354 Alamy Liu
0 0 0 0 6
354 fanoush
0 0 1 1 1
354 Akos Vandra
0 0 0 0 6
472 Mahavir Jain
0 0 0 0 5
472 Tim 'mithro' Ansell
0 0 0 0 5
472 Thomas Hebb
0 0 0 0 5
472 Pavel I. Kryukov
0 0 0 1 3
472 Michael Schwingen
0 0 0 0 5
472 Karl Kurbjun
0 0 0 0 5
472 Hongren Zheng (Zenithal)
0 0 0 1 3
472 Aurelien Jacobs
0 0 0 0 5
472 Jonathan McDowell
0 0 0 0 5
Showing 461 to 480 of 1255 results
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Contributing Companies

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