RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,195 commits
1,232 contributors

Rank

193 7

Started

2006-06-02 6,977 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 147 commits #347 25 contributors #290
Past 90 days 387 commits #441 55 contributors #253
Past 365 days 1,539 commits #499 179 contributors #214
Past 1095 days 7,004 commits #372 450 contributors #205
All time 25,195 commits 1,232 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
450 Columbus240
0 0 0 0 5
450 Hongren Zheng (Zenithal)
0 0 0 1 3
450 Josh Scheid
0 0 0 0 5
450 Eric Wetzel
0 0 0 0 5
450 Austin Morton
0 0 0 0 5
450 Zakk Chen
0 0 0 1 3
450 Han-Kuan Chen
0 0 0 0 5
450 Ben McMorran
0 0 0 1 3
450 Mahavir Jain
0 0 0 0 5
450 Szymon Modzelewski
0 0 0 0 5
450 Tim 'mithro' Ansell
0 0 0 0 5
450 Thomas Hebb
0 0 0 0 5
450 Michael Schwingen
0 0 0 0 5
474 Dan Mangum Upbound
0 0 0 0 4
474 Hanna Kruppe
0 0 0 0 4
474 Girts
0 0 0 0 4
474 Chris Kilgour
0 0 0 0 4
474 Diego Herranz
0 0 0 0 4
474 Jonathan Neuschäfer
0 0 0 1 2
474 Kyle Manna
0 0 0 0 4
Showing 461 to 480 of 1232 results
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Contributing Companies

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