RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
25,984 commits
1,254 contributors

Rank

193 13

Started

2006-06-02 6,918 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 100 commits #494 28 contributors #261
Past 90 days 369 commits #501 70 contributors #204
Past 365 days 1,607 commits #474 189 contributors #202
Past 1095 days 6,969 commits #375 454 contributors #203
All time 25,984 commits 1,254 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
354 Peter Mamonov
0 0 0 0 6
354 Mukund
0 0 1 1 1
354 Matthijs Kooijman
0 0 0 2 2
354 Luke Lau
0 0 1 1 1
354 Julien Massot
0 0 0 0 6
354 Hans Boehm
0 0 0 2 2
354 Christian Eggers
0 0 0 0 6
354 Attila Kinali
0 0 0 0 6
354 Atish Patra
0 0 0 0 6
354 Matt Trescott
0 0 1 1 1
354 Bill Traynor
0 0 0 2 2
354 François LEGAL
0 0 0 2 2
354 Eric Biggers
0 0 1 1 1
354 eolson
0 0 0 2 2
354 Jiafei Pan
0 0 1 1 1
354 Alexandre Ghiti
0 0 0 2 2
354 Alan Bowman
0 0 0 0 6
354 Alamy Liu
0 0 0 0 6
354 Akos Vandra
0 0 0 0 6
354 John Zaitseff
0 0 0 2 2
Showing 401 to 420 of 1254 results
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Contributing Companies

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