RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,245 commits
1,237 contributors

Rank

209 9

Started

2006-06-02 6,995 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 88 commits #557 28 contributors #251
Past 90 days 377 commits #443 59 contributors #238
Past 365 days 1,482 commits #508 174 contributors #224
Past 1095 days 7,011 commits #371 446 contributors #210
All time 25,245 commits 1,237 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
137 Will Dietz SiFive
1 2 2 2 2
142 james-ball-qualcomm
0 0 4 4 4
142 liangzhen
0 0 3 5 5
142 Samuel Obuch
0 0 4 4 4
142 Nathaniel Wesley Filardo
0 0 4 4 4
146 Andrey Smirnov
0 0 0 0 23
146 Tsukasa #01 (a4lg)
0 0 0 2 19
146 Jia-Wei Chen
0 2 2 3 3
146 Andrey Yurovsky
0 0 0 0 23
146 Xu, Zefan
0 2 2 3 3
146 Nemui Trinomius
0 0 0 0 23
152 Peter R Herrmann
0 1 2 4 4
152 Karl Palsson
0 0 0 1 20
152 Antony Pavlov
0 0 0 0 22
155 Kevin Broch
0 0 0 7 7
155 Steven Stallion
0 0 0 0 21
155 Robert Jordens
0 0 0 0 21
155 Freddie Chopin
0 0 0 0 21
155 Carl Friedrich Bolz-Tereick
1 1 2 2 2
155 Albert Ou
0 0 0 0 21
Showing 141 to 160 of 1237 results
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Contributing Companies

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