RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
efabless
SiFive
Tenstorrent
Ventana Micro Systems
started in 2006
25,873 commits
1,246 contributors

Rank

187 21

Started

2006-06-02 6,900 days ago

Open Core Products

efabless efabless
SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems

GitHub Stars

8,179 #1,437

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 126 commits #422 30 contributors #246
Past 90 days 343 commits #529 62 contributors #233
Past 365 days 1,638 commits #461 189 contributors #200
Past 1095 days 6,972 commits #376 453 contributors #201
All time 25,873 commits 1,246 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
470 respasa
0 0 0 0 5
470 Zakk Chen
0 0 0 1 3
470 Ben McMorran
0 0 0 1 3
470 Mahavir Jain
0 0 0 0 5
470 Tim 'mithro' Ansell
0 0 0 0 5
470 Rémi PRUD'HOMME
0 0 0 0 5
470 Piotr Kasprzyk
0 0 0 1 3
470 Michael Schwingen
0 0 0 0 5
470 Karl Kurbjun
0 0 0 0 5
470 Hellosun Wu
0 0 0 0 5
491 Paul Wise
0 0 0 0 4
491 Markus Reiter University of Innsbruck
0 0 0 0 4
491 Liming Sun
0 0 0 0 4
491 Dan Mangum Upbound
0 0 0 0 4
491 Hanna Kruppe
0 0 0 0 4
491 Girts
0 0 0 0 4
491 Chris Kilgour
0 0 0 0 4
491 Diego Herranz
0 0 0 0 4
491 Jonathan Neuschäfer
0 0 0 1 2
491 Kyle Manna
0 0 0 0 4
Showing 481 to 500 of 1246 results
Previous Next

Contributing Companies

Add the OSSRank badge to this project

OSSRank Badge Add this OSSRank shield to your project's README.md
[![OSSRank](https://shields.io/endpoint?url=https://ossrank.com/shield/1311)](https://ossrank.com/p/1311)