RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,232 commits
1,235 contributors

Rank

198

Started

2006-06-02 6,990 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 101 commits #476 27 contributors #262
Past 90 days 378 commits #442 55 contributors #252
Past 365 days 1,497 commits #506 176 contributors #224
Past 1095 days 7,008 commits #372 446 contributors #209
All time 25,232 commits 1,235 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
472 Lehua Ding
0 0 0 1 2
472 Patrick Stewart
0 0 0 0 4
472 Trevor Woerner
0 0 0 1 2
472 Tormod Volden
0 0 0 0 4
472 Tom Rini
0 0 0 0 4
472 Taras Kondratiuk
0 0 0 0 4
472 Steve Bennett
0 0 0 0 4
472 Seth LaForge
0 0 0 0 4
472 Paul Wise
0 0 0 0 4
472 Rocco Marco
0 0 0 1 2
472 Markus Reiter University of Innsbruck
0 0 0 0 4
472 Liming Sun
0 0 0 0 4
472 Dan Mangum Upbound
0 0 0 0 4
472 Anders
0 0 0 0 4
472 Hanna Kruppe
0 0 0 0 4
472 Girts
0 0 0 0 4
472 Chris Kilgour
0 0 0 0 4
472 Diego Herranz
0 0 0 0 4
472 Jonathan Neuschäfer
0 0 0 1 2
472 Kyle Manna
0 0 0 0 4
Showing 481 to 500 of 1235 results
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Contributing Companies

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