RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,232 commits
1,235 contributors

Rank

198

Started

2006-06-02 6,989 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 101 commits #476 27 contributors #262
Past 90 days 378 commits #442 55 contributors #252
Past 365 days 1,497 commits #506 176 contributors #224
Past 1095 days 7,008 commits #372 446 contributors #209
All time 25,232 commits 1,235 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
336 Eric Biggers
0 0 1 1 1
336 david-henley
0 0 1 1 1
336 Alan Bowman
0 0 0 0 6
336 Alamy Liu
0 0 0 0 6
336 Akos Vandra
0 0 0 0 6
336 Sofiane HAMAM
0 0 1 1 1
336 John Zaitseff
0 0 0 2 2
448 Eric Wetzel
0 0 0 0 5
448 Zakk Chen
0 0 0 1 3
448 Han-Kuan Chen
0 0 0 0 5
448 Ben McMorran
0 0 0 1 3
448 Mahavir Jain
0 0 0 0 5
448 Tim 'mithro' Ansell
0 0 0 0 5
448 Thomas Hebb
0 0 0 0 5
448 Michael Schwingen
0 0 0 0 5
448 Karl Kurbjun
0 0 0 0 5
448 Hongren Zheng (Zenithal)
0 0 0 1 3
448 Austin Morton
0 0 0 0 5
448 Aurelien Jacobs
0 0 0 0 5
448 Jonathan McDowell
0 0 0 0 5
Showing 441 to 460 of 1235 results
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Contributing Companies

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