RISC-V

An open standard instruction set architecture (ISA) based on established RISC principles

Computer Architecture
SiFive
Tenstorrent
Ventana Micro Systems
efabless
started in 2006
25,261 commits
1,238 contributors

Rank

215 16

Started

2006-06-02 6,998 days ago

Open Core Products

SiFive Core IP SiFive
Grayskull Tenstorrent
Ventana Ventana Micro Systems
efabless efabless

GitHub Stars

8,179 #1,436

Weekly commits since inception
2006 2015 2025

Weekly contributors since inception
2006 2015 2025

Recent Project Activity

Time Period Commits Contributors
Past 30 days 83 commits #604 27 contributors #265
Past 90 days 372 commits #453 59 contributors #238
Past 365 days 1,492 commits #511 175 contributors #222
Past 1095 days 7,024 commits #370 447 contributors #210
All time 25,261 commits 1,238 contributors

Contributing Individuals

Contributor 30 days 90 days 365 days 1095 days All time
217 Andreas Bolsch
0 0 0 1 11
217 Shaked Flur
0 0 0 0 13
217 Drasko DRASKOVIC
0 0 0 0 13
217 Sean Anderson
0 0 0 1 11
225 Aaron Durbin
0 0 0 4 4
225 Noah Moroze
0 0 0 4 4
225 Martin Schoeberl
0 0 2 2 2
225 Peter Rugg
0 0 1 1 7
225 Peter Lawrence
0 0 0 1 10
225 Maciej Pijanowski
0 0 0 0 12
225 Edgar Grimberg
0 0 0 0 12
225 bodylove
0 0 0 0 12
225 Martin Maas
0 0 2 2 2
225 Andrei Lalaev
0 0 1 3 3
225 Alex Bradbury
0 0 0 2 8
225 Pete Moore
0 0 2 2 2
225 Ondřej Hošek
0 0 2 2 2
225 Adam Novak
0 0 2 2 2
225 Nico Pitre
0 0 0 0 12
225 Alexander Kurz
0 0 0 0 12
Showing 221 to 240 of 1238 results
Previous Next

Contributing Companies

Add the OSSRank badge to this project

OSSRank Badge Add this OSSRank shield to your project's README.md
[![OSSRank](https://shields.io/endpoint?url=https://ossrank.com/shield/1311)](https://ossrank.com/p/1311)